VCA theory question

[juniorhifikit]

Originally I had posted this as my buffer circuit:

But now I'm questioning why I'm connecting the outputs of the buffer amps to the CV ports AND in parallel to ground? Maybe this makes more sense:

[JR.]

[juniorhifikit]

So, the scale of the CV (from 0 - 5v down to 0 - .776v) with the voltage follower is determined by the total series resistance of R6 + R5 + R4?

[juniorhifikit]

I had taken the filtering off the opamp outputs, but Eagle left nets in their place... oops

[JR.]

So, the scale of the CV (from 0 - 5v down to 0 - .776v) with the voltage follower is determined by the total series resistance of R6 + R5 + R4?

the EC- is defined by the resistor divider as if R4 was connected to ground (opamp - input is a virtual ground) and R5+R8 are one resistor. EC+ is simple unity gain inverter with mirror image inverted version of voltage at top of R4. While it isn't labeled R4 should be 2k just like R3.

From observation I would be tempted to swap the values of C4 and C5.. the digital LPF is mainly to remove digital noise (spikes). While filter at VCA is to reduce all noise... If you are also using c4 to define a rate of change slope for control voltages maybe make both caps large.

JR

[juniorhifikit]

the EC- is defined by the resistor divider as if R4 was connected to ground (opamp - input is a virtual ground) and R5+R8 are one resistor. EC+ is simple unity gain inverter with mirror image inverted version of voltage at top of R4. While it isn't labeled R4 should be 2k just like R3.

To scale the 5V DAC output down to less than a volt, I need to have less than unity gain at the buffer output, no? The THAT example shows an input voltage of 4.98V x 2K (fbk R) / 6.34k + 6.49K (total input R), which gives us the .788 volts.

From observation I would be tempted to swap the values of C4 and C5.. the digital LPF is mainly to remove digital noise (spikes). While filter at VCA is to reduce all noise... If you are also using c4 to define a rate of change slope for control voltages maybe make both caps large.

JR

Since I DO want to filter the CV change rate, I could make both caps 2.2uF, but I'm not sure what cutoff the filter should be set to, in addition to calculating the R of the two-stage filters, and the R of the voltage divider for the voltage follower stage, I'm not sure how to calculate it all...

[JR.]

The math for calculating a voltage step is e^(-t/RC)...

For approximation, 1 time constant gets you to 60-70% of final result, 3 time constants 95% of final result.

With two large caps and 3 resistors in series, it's a little more complex as the two C load each other, so they don't simply add (not twice as long as 1 RC, maybe 1.5x or so for similar values).

Some things are easier to dial in on the bench.

JR

[juniorhifikit]

I think I have the right formulas, I just don't know what to solve for What is a good cutoff frequency to filter the digital noise at the DAC output?

The second filter is for timing, and THAT have suggested 7mS with an RC of 6K34 and 2.2uF. If I made the first filter for the DAC output the same as the second timing filter, the voltage divider at R4 would have to be 2.34K Ohms according to my calculations in order for the voltage follower stage to scale 4.98V down to .776V

R2 = R1 / (Vin/Vout - 1)
or
R2 = (6.34K + 6.34K) / [(4.98/.776) - 1] = 2.34K


Actually, since I'm doing bipolar CV, I need half that .776 voltage on each port, so R2 would be 1.07K (or there about). If that seems right, I guess I'm off to the bench...

[JR.]

That looks about right fir R divider.

The mental calculation for digital output filter is it certainly can't be less than overall 7 mSec...

trade off is lower the digital pole the more digital ground gets coupled into CV.

I would avoid overanalyzing this one decision,,, a six of one half dozen another..

how about 1 mSec??

JR

[juniorhifikit]

So, the bread boarded buffer circuit behaves as expected: the 4.98V are buffered down to around plus and minus 390mV, which added together is roughly the 780mV max the VCA's control port can see (split in half for bipolar control). Now I need to bias each CV down by around 355mV on each port to give me around 35mV on each CV port, which when added together will be roughly 70mV or +12dB of VCA gain at the DAC's max 4.98V output (exactly what I want).

I simply drew in R7 & R8 to represent that I need to bias my control voltage, but I'm wondering what the best way would be to accomplish this? Could I just use a trim pot to peel off a little V+ and V- and just add it to the output of each buffer opamp like this?