FPGA Design...

[JR.]

To the extent that the charge injection is symmetrical and at a super audible rate it should cancel out, but yes if the impedances are large the charge could be significant in the short term. If there is an up/down time dependent component, or perhaps a terminal voltage dependent component to the charge injection, that could cause an error.

DA of the caps could also be an issue when commutating the termination impedance so use quality film caps.

You may want to look into S/H technology for some similar concerns.

HF switching and high impedances don't seem like a great combination, but YMMV so good luck.

JR

[Crusty]

Thanks guys. When I have time, I'll lash up a pulse generator, wire up a breadboard and see what happens...

[jdbakker]

The HPSDR project (ham-driven software defined radio) has spawned a simple hands-on Verilog class. Might be worth checking out, especially if you have a background in programming in C. Have a look at http://verilog.hpsdr.org/ for the video files and a few more useful tools.

Now to get 16b resolution at a super audible rate you need a >1GHz clock which isn't going to happen in cheap micro, but you can probably get 10b or so range.

If you go with straight PWM, yes. Better results can be achieved by building a sigma/delta modulator in the FPGA (or in software), so the switching noise predominantly falls outside the audio band. You could also try a simple LFSR as a modulator; these are especially easy to implement and work reasonably well as long as you stay away from the control range extremes (full-on/full-off). I believe we discussed this at The Other Place.

EDIT: Yes we did, and it even had the same goal (modulating a resistor).

JD 'late to the party' B.

[JR.]

Thanks I need to wrap my head around alternatives to simple PWM. I am constantly bumping into practical limits of resolution and PWM period in my current platform.

JR